The present invention relates to semiconductor devices and a process for their manufacture. The invention is illustrated by an example with regard to the manufacture of a raised source/drain MOSFET, and more particularly to the manufacture of an improved shallow junction MOSFET. However, it will be recognized that the invention has a wider range of applicability. For example, the invention may be applied in the manufacture of other semiconductor device such as CMOS, EPROM, logic circuits to raise the height of their doped regions for the convenience of forming the contact hole and salicide process.
Methods of manufacturing metal-oxide semiconductor field effect transistors (MOSFET) are well know in the art. For economic reasons, the smaller the dimension of the device, the more circuits can be formed in one chip and more devices can be made in one wafer. The current trend in the semiconductor industry has evolved to increase the dimension of the wafer used to manufacture the devices and to reduce the dimensions of the device.
During research on miniaturization, consideration was given to narrowing the gate width of the MOSFET. If all the design conditions are kept the same but the gate length is decreased, the channel (the distance between the source and drain) will overlap with the depletion regions of the source and drain which will lead to the short channel effect and increase sub-threshold current Id. See FIG. 1A.
The Sub-threshold Current is defined as the current passing the channel from drain to source when the gate voltage is smaller than the threshold voltage. In the other words, the sub-threshold current is the current when the MOSFET is "Off".
The motions or movement of the carriers in a semiconductor circuit can be separated into two modes; the drifting and the diffusion modes. The former is caused by the electrical field; and the latter is related to the temperature of the carriers. In a N type MOSFET, the motion of carriers is under the drifting mode when the gate voltage is higher than the threshold voltage and when the applied gate voltage is lower than the threshold voltage, the situation will change to the diffusion mode. By the nature of the carrier motion, the NMOS can be seen as a npn Bipolar Junction Transistor (BJT) having the structure "source-channel-drain" whose PN Junction between source and channel is under forward bias and the junction between channel and drain is under reverse bias so that the NMOS acts as a npn BJT. The electrons will flow from source to drain. The sub-threshold current Id is the sum-up of these electrons.
FIG. 1B shows the curves of Id related to gate voltage. It can be seen that with the decline of channel length, the sub-threshold current Id will increase. When the channel length is less than 1 um, the sub-threshold current will have a huge growth because more electrons are injecting from the source into the channel. This situation allows the operation mode of NMOS to approach or equal the active mode, even the gate voltage is smaller than the threshold voltage which means that the gate electrode has lost the ability to act as a control switch.
A highly concentrated doped substrate is used to solve the problem by limiting the depletion region diffusing into the channel. Another method for reducing the sub-threshold current is to minimize the cross section area of the channel for the scaled relationship between Id and the area which leads to the new diffusion technique: Shallow Junction MOSFET Manufacture.
Although the use of a shallow junction will solve the problem, other disadvantages happen during contact hole forming and salicide processing. Unavoidably, the source/drain regions are attacked during the contact hole etching and salicide formation. For the ultra shallow junction, over etching will cause a concave bowl in the junction which allows the contact plug to be closer to the junction edge which leads to a current leakage increase. Moreover, it may etch through the junction and destroy the transistor.
The most focused approach is to deposit a buffer conductive layer on the source/drain regions to increase the thickness so that the selective epitaxial growth (SEG) process was shown to form a raised source/drain device. The SEG process was carried out under reaction conditions at 600.about.650 degrees centigrade with 1.about.2 SCCM Si2H6 gas discussed in the paper, "RA High-Performance 0.1 um CMOS with Elevated Salicide using Novel Si-SEG Process" by Hitoshi Wakabayashi & Toyoji Yamamoto & Toru Tatsumi & Ken'ichi Tokunaga & Kakao Tamura & Tohru Mogami and Takemitsu Kunio, IEDM, 1997.
The SEG process offers a method to fabricate raised source/drain regions, but the equipment used in the SEG process is not readily available, it is not mass produced equipment so that most IC-Fabricators do not have this SEG equipment. From the above, it is seen that a raised source/drain regions MOSFET manufacturing process with mass production capability is desired in the deep sub-micro semiconductor technique. Further, once the shallow junction technique is applied to various kinds of devices such as CMOS, Flash and EEPROM, a process for raising doped regions will also be needed.